The future of the PCIe interconnect bus

It is hard to believe there was once a time when there was not PCI Express or any of its Peripheral Component Interconnect progenitors. Shortly after the Intel x86 architecture exploded into the market place in the mid-1970s, all there was in the many homebrew personal computers and single board computers developed for industry was the S-100 bus, originally nothing more than the pins of the Intel 8080 run out onto the backplane to form the single system bus.

But after about five years its dominance evaporated. In 1981 IBM bulldozed its way into the one computing market segment it did not dominate - personal computing - with the IBM PC AT and its Industry Standard Architecture (ISA), which also quickly became widely used in embedded single board computing.

ISA’s dominance as well was short lived. By 1987, Intel engineers developed the PCI bus to replace it. And now, remarkably, 25 years later, PCIe dominates virtually every segment of computing where a high performance interconnection bus is necessary.

Part of its longevity is the flexibility of the original PCIe specification and the foresight of the engineers who developed it. But much is also owed to the companies that make up the PCI SIG, who have adapted and extended the standard into a wide range of applications. In addition to the recent design articles included in this week’s Tech Focus newsletter, other articles that reflect its flexibility and usefulness to developers include:

• Making the shift to optical interconnect with PCIe Gen3
• Why PCIe-Based Systems Need Multicast
• Using multi-root (MR) PCIe to extend nextgen multi-host switch fabrics
• Using an interface wrappers to simplify implementing PCIe on FPGAs

Indicative of the ubiquity and vitality of the PCIe bus across the embedded system infrastructure are some recent conference and technical journal papers I have come across, including:

• Speedy bus mastering with PCI Express
• A PCIe Hot-Plug mechanism for a Linux ATCA control system
• Bus mastering PCI Express in an FPGA
• Direct GPU/FPGA communication via PCI Express

This is not to say that PCIe does not have its limitations and is not without serious competitors in many important segments of the market. In “Sub-microsecond interconnects: PCIe, RapidIO and other alternatives,” Sam Fuller makes the important observation that much as there are different forms of processors that are optimized for differing applications, interconnects are also designed and optimized to solve different connectivity problems.

“Typically an interconnect will solve the problems it was designed for very well and can be pressed into service to solve other problems, but it will be less efficient in these applications,” he writes. Technologies such as PCI Express and 10G Ethernet are certainly not going away any time soon, according to Fuller, but they also will not be the foundation for future tightly coupled computing systems.

As the systems you are designing move to applications requiring faster and more reliable high speed interconnects, you will no doubt be considering a variety of high speed, low latency alternatives. I would like to hear from you in the form of comments on the site, emails, contributed articles or blogs about how you are addressing these issues.

You May Want to Know:

Structure of PCI Express Bus

How to Install a PCI Express NIC Card

PCIe 4.0 Bandwidth and Speed

How PCI Works

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