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PCIE Server NIC card Application

  • PCI-E NIC Cards provide redundant connectivity to ensure an uninterrupted network connection.

  • PCI-E NIC Cards are ideal for VM environments with multiple operating systems, requiring shared or dedicated NICs.

  • They are specially designed for desktop PC clients, servers, and workstations with few PCI Express slots available.


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PCIe 4.0 Bandwidth and Speed

After technical analysis, PCI-SIG determined that 16 GT/s on copper is technically feasible for the PCIe 4.0 specification bit rate. This means a doubled bandwidth over the PCIe 3.0 specification’s 8 GT/s bit rate, a challenge PCI-SIG has consistently met with each specification generation (Figure 1). Additionally, by continuing to use copper as the physical medium for its specifications, PCI-SIG can help keep costs down for its members.

Figure 1 PCIe specification bandwidth capabilities have consistently doubled from generation to generation.


While doubling the data rate, the PCIe 4.0 architecture will maintain its position as a low-cost, high-performance I/O technology. The PCIe 4.0 specification will enable high-end implementations, such as servers, to get the higher bandwidth and faster speeds that they require, while providing cost-sensitive devices, such as tablets, power and space savings.
For tablets and other devices with short channels, manufacturers will be able to implement PCIe 4.0 technology without the addition of re-drivers. For those applications that require more bandwidth, have longer channels and are not cost-sensitive, re-drivers can be utilized to deliver the 16 GT/s. The PCIe 4.0 specification strikes the right balance between delivering needed bandwidth and keeping costs low.
Using the PCIe 4.0 architecture, designers can double their bandwidth by converting from PCIe 3.0 to 4.0 technology. However, in this conversion designers will maintain the same amount of power usage as seen in their 3.0 implementations. For example, a PCIe 3.0 x8 device running as a PCIe 4.0 x8 device should have the same amount of power utilized but would benefit from the PCIe 4.0 technology advancements. PCI-SIG is also investigating advancements in active and idle power optimizations, which are key issues facing the industry today.
For even further power savings, designers can reduce the I/O pin width. For tablets, this means they could utilize the same bandwidth of a PCIe 3.0 device by adopting PCIe 4.0, but only use half the pins—therefore saving power. Designers can decrease the architecture’s power utilization by reducing the number of I/O pins, which translates directly to power and cost savings. In the PCIe 4.0 architecture, this is made possible by improvements to the PHY-layer. For the PCIe 4.0 architecture PHY-layer, users will experience improved jitter performance, Rx return loss, Tx bandwidth and frequency. Overall, the goal is to allow the design to maintain power requirements relative to PCIe 3.0, even though the performance is clocking at double the frequency.
Backward compatibility is a foundational requirement set by PCI-SIG for the PCIe architecture. PCIe 4.0 technology will maintain backward compatibility with previous PCIe generations and provide a design point for high-volume platform I/O implementations across a wide range of existing and emerging applications. While maintaining compatibility with previous generations of PCIe architecture, a 16 GT/s interconnect can also be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure. Basically, all 3.0 devices will still be able to talk to 4.0 devices—a crucial factor in the long history of success for PCIe specifications—and motherboard and adapter vendors will be able to release solutions independent of one another.

You May Want to Know:

How PCI Works

Adding a PCI Device

Applications of PCI Express

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Gigabit Single SFP Slot PCI-E 2.0 Server Adapter Card