Secondary or Niche PCIe Applications

After we read the “Priimary PCIe Applications”, now, let’s read the “Secondary or Niche PCIe Applications”

Systems in the first tier of enterprise networks and in the access tier of wide area networks (WANs) often employ only a small number of line interface protocols on their downstream (user-facing) ports and one protocol on their upstream port(s). This decision is often dictated by tight cost constraints that place limits on the system’s complexity or by the physical reach limits of the protocol the system supports. Such systems will maintain the data in as close to its native form as possible and perform most translation and data processing on the uplink card (see figure 1). PCIe will usually not be used in these types of systems. 

However, in applications that interwork multiple protocols, such as in aggregation and edge nodes, there is no obvious format for internal data transfers. Interworking implementations logically terminate the connection on the ingress interworking device (usually a CPU, NPU, or ASIC) and then generate a new connection to the egress interworking device, which in turn terminates and generates its own new connection on the output port.

Figure 1 Central processing architecture

 

On-card data planes tend to use point-to-point protocols based around blocks of data and do not need routing headers. Usually designers employ a standards-based physical or transport protocol and perform higher layer functions with a proprietary protocol on either end of the link. One example of this approach would be the use of XAUI physical specs, MAC-based framing, and proprietary packet headers between two ASICs. The non-standardized nature of these protocols is a significant liability.

Figure 2 PCIe in an on-card data plane application

Figure 3 PCIe in a low-end router

 

Given the high availability requirements of most communications systems, functions controlling 

the system must have access to every module in the system regardless of what is happening on the data plane. Historically, designers have addressed this need by using physically separate pathways across the backplanes of their systems or within highly complex individual cards (see figure 1 and figure 4).

 

Figure 4 Distributed processing architecture

 

PCs and servers have traditionally used a single plane for both control and data movement functions. While there remains a high degree of commitment in the communications industry to physically separate control and data planes, this merged control and data plane architecture 

may become increasingly acceptable for several reasons:

 

1.  Backplane switches are now capable of maintaining traffic separation (security).

2.  Backplane switches can guarantee high-priority traffic will get through even if there is a 

denial-of-service attack on lower priorities (guaranteed access).

3.  As PC architectures penetrate further into the communications segment, there will be more 

system and chip architectures that don’t support the separation (supply of components).

4.  The cost contribution of maintaining two fabrics, each with its own redundant elements 

(fabric management SW) and mean time between failures (MTBF), is high.

 

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