Primary PCIe Applications

The adoption of the original PCI protocol in PCs and servers paved the way to the widespread availability of components with PCI interfaces for communications systems. While early device development focused on typical PC components such as Ethernet network interface card (NIC) chips, PCMCIA card controllers, and disk controllers, the bus eventually became the protocol of choice for CPU ports on almost all communications devices including framers and NPUs. Given the performance, low cost, and supporting ecosystem the PCI interface offers, this trend will likely continue with PCIe. 

Moreover, PCIe offers an additional compelling advantage—low pin count. While a CPU port required 47 signal pins to implement PCI 33/32, it needs only four pins to support an x1 PCIe port. Even though the new interface uses higher speed signals, its reduced pin count and its impact on board layout, routing, and connector design will prove highly attractive to board designers.

HBA Card

Control plane accesses to devices usually involve access to registers or the movement of blocks of data into and out of memory. This function is well suited to the memory-based paradigm used in PCIe. In addition, designers of control plane functions within a card tend to use a hierarchical model where a single housekeeper CPU manages each individual device on the card. This approach is also well matched to the PCIe model. Finally, traffic patterns in a control plane on a single card are almost exclusively between the housekeeper CPU and each individual device, rather than peer to peer between devices. 

While PCIe allows multiple priorities of traffic, control plane traffic within a single card is usually low enough in bandwidth to avoid the need to segregate different types of traffic from one another. Over time, designers will migrate from current CPU port protocols on communications cards.

Figure 2 Line card partitioning options

One of the most common customizations in any communications system is selection of I/O. For this reason, line interfaces are often packaged on their own modules. Depending on the system type, this configuration may be limited to the physical aspects of the I/O or allow selection of a number of different protocols. In the first case, users often wish to select or change features like the physical connector type, optical frequency, or output power. In some systems, packaging decisions may dictate separating the line driver/receiver and connectors into a removable module (see option b in figure 2). Other architects may choose to partition their system in a similar way to simplify maintenance, since the line driver often exhibits the highest failure rate.

Some designers will decide to include a framer function with those components on a single removable module (see option c in figure 2). This strategy allows the customer to select not just the reach and frequency of the interface, but also the protocol supported (e.g., ATM over SONET vs. packet over SONET). Again, the architect may partition the system in this manner to simplify component replacement and manage module failure rate estimates.

Conceptually, both of these approaches are an extension of the on-card control plane model that PCIe supports so well. The long reach and low pin count of the interconnection make this approach even more attractive. It should be noted that this paradigm also applies to cards that hold relatively intelligent data plane elements such as I/O processors, digital media adapters (DMAs), NPUs, and ASICs. The test is how much general-purpose processing capability such an element provides on the module. In many of these types of systems, the designer will use a PCI Express switch on the local module to fan out the PCIe connection to as many devices as the system requires.

Figure 4. Central Processing Architecture

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