Basic Info of PCI Family

The PCI family was originally designed to provide a standards-based expansion bus within personal computer architecture. The architecture supports up to six plug-in modules (with the seventh entity being the motherboard), and its electrical characteristics define a copper-based interconnect that runs across connectors.

The original PCI specification also assumed that a single CPU complex would manage setup (enumeration) of all other modules. This assumption dictated that the addressing scheme would be a direct one, with only one shared address space throughout. 

PRO/1000 PT Dual Port Server Adapter

However, the designers did reserve some of the bits of the addressing to support bridge entities. While the overall scheme assumes that the majority of all traffic runs from the master CPU, peripheral devices can access one another in a peer-to-peer fashion over the interconnect.

Figure 1 Comparative bidirectional bandwidth chart

Figure 1 and table 1 illustrate the relative speed of members of the PCI family of interconnects and compare their key characteristics to some other familiar interconnects.

Table 1.  Characteristics of key interconnects

As the most recent addition to the PCI family of protocols, PCIe embodies all the concepts embedded in earlier versions, with a few minor exceptions. Instead of a parallel topology, however, it uses a serial point-to-point approach. Table 1 illustrates how, as the PCI family has evolved, designers have traded off increases in speed against signal reach and the number of interconnected entities. PCIe takes the next evolutionary step in this process by introducing a switch for interconnecting entities. However, it also supports a longer reach for signals and, with the assistance of the switch, increases the number of connected entities.

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