- Fiber Optic Transceiver
- High Speed Cable
- Fiber Optical Cable
- Fiber Optical Patch Cords
- Splitter CWDM DWDM
- PON Solution
- FTTH Box ODF Closure
- PCI-E Network Card
- Network Cables
- Fiber Optical Adapter
- Fiber Optical Attenuator
- Fiber Media Converter
- PDH Multiplexers
- Protocol Converter
- Digital Video Multiplexer
- Fiber Optical Tools
- Can SFP+120KM be available? ...
- Why the price has so huge di...
- Can XFP transceiver modules ...
- Must optical fiber jumper be...
- Is there a module which can ...
- Can different brands SFP tra...
- How long will you change you...
- The difference between DDM S...
- Comparison of EPON and GPON
- Should we use 3rd party’s ...
- How to make differences betw...
- How to Choose A Right Fusion...
- Why Using a Compatible SFP O...
- Optical fiber transmission l...
- How to Use Fiber Media Conve...
- Fiber jumper wire of web-cla...
- The fiber’s end face and d...
- What are simplex, half duple...
- Comparison of PC, UPC and AP...
- Where can optical fiber jump...
FPGA, Characteristics, Applications, Manufacturers
FPGA (Field-Programmable Gate, the Array), field programmable gate array, it is PAL, GAL, CPLD and other programmable devices on the basis of the further development of the product. It appears as the field of application specific integrated circuit (ASIC) in a semi-custom circuit, which addresses the lack of custom circuits, but also to overcome the original programmable devices gate a limited number of shortcomings.
Hardware description language (Verilog or VHDL), circuit design, can be subjected to simple
Single comprehensive layout, fast burn to the FPGA for testing, the mainstream of modern IC design verification technology. These editable components can be used to implement some of the basic logic gates (AND, OR, XOR, NOT) or a more complex combination of functions such as decoders or mathematical equations. Inside most of the FPGA, memory devices such as trigger (Flip-the flop) or a more complete memory block also contains editable components.
System designers can through the editable connections within the FPGA logic blocks connected together like a breadboard was placed on a chip. A factory finished FPGA logic blocks and connections can be changed in accordance with the designer, so the FPGA can complete the required logic function.
FPGA Generally speaking, slower than the speed of the ASIC (application specific integrated chip), unable to complete a complex design, but also consume more power. But they also have many advantages such as can be quickly finished, you can modify the program to correct errors and cheaper cost. Editing capability FPGA vendors may also offer cheap. Because these chips are relatively poor editing capabilities, the development of these designs is, in the ordinary FPGA design will transfer to one similar to the ASIC chip. Another method is to prepare the CPLD (complex programmable logic device).
CPLD and FPGA
As early as the mid-1980s, the FPGA has been rooted in the PLD device. CPLDs and FPGAs, including a relatively large number of programmable logic unit. CPLD logic gate densities between a few thousand to tens of thousands of logic cells, while the FPGA is usually in the tens of thousands to several million.
The main difference of CPLD and FPGA is the structure of their system. The CPLD is a somewhat restrictive structure. This structure results from one or more editable and logical set of columns and some relatively small amount of the lock register. This results in the lack of editing flexibility, but there is the delay time can be expected and logical unit to connect the advantages of a high percentage of the unit. While the FPGA is the connection unit, so it can be more flexible editing, but the structure is more complex.
CPLD and FPGA Another difference is that most FPGAs contain a high level of built-in module (such as adder and multiplier) and the built-in memory. Therefore, one important difference is that a lot of new FPGA supports full or part of the system re-configuration. Allow their design to change with the system upgrade, or dynamic reconfiguration. Some FPGA allows part of the equipment to re-edit the other parts continue to operate normally.
FPGA uses a logic cell array LCA (Logic Cell Array), such a concept, and the internal configurable logic block CLB (Configurable Logic Block), input-output module of IOB (Input Output Block), and internal connections (Interconnect) three parts. The field programmable gate array (FPGA) are programmable devices. Compared with the traditional logic circuit and gate array (such as PAL, the GAL and CPLD devices), has a different structure to the FPGA, the FPGA use small lookup table (16 the × 1RAM) to implement the combinational logic, each lookup table connected to a D flip-flop the input of the flip-flop again drive other logic circuits or drive I / O, which constitutes the basic logic unit module can achieve the combinational logic function can be sequential logic functions, these modules between the metal lines connected to each other or connected to I / O modules.
FPGA logic is loaded to the internal static memory cell programming data, the values stored in the memory unit determines the connection mode between the logical unit of logic functions, as well as the module or modules and I / O, and the final decision FPGA can realize the function, the FPGA allows an unlimited number of programming.
Type of FPGA used in power
FPGA power requirements of the output voltage range from 1.2V to 5V, output current range from tens of milliamps to several amps. Available three kinds of power: Low Dropout (LDO) linear regulators, switch-mode DC-DC regulator and switch-mode power supply module. The final choice of what kind of power depends on the system, budget and time to market requirements.
If board space is a primary consideration, low output noise is very important, or the system to respond quickly, you should use the LDO regulator input voltage variations and load transients. LDO efficacy is relatively low (because it is a linear regulator), can only provide the low output current. The input capacitance can usually reduce inductance and noise of the LDO input. LDO output capacitors to handle the system transients, and to maintain system stability. You can also use the dual output LDO VCCINT and VCCO supply.
If efficiency is essential in the design, and system requirements for high output current, the switching regulator dominant. The effectiveness of the switching power supply higher than the LDO, but a switching circuit will increase the output noise. And the LDO, switching regulator inductor DC-DC converter.
FPGA-specific power requirements
To ensure correct power-on, The VCCINT core voltage ramp time must be within the scope specified by the manufacturer. Some of the FPGA the VCCINT will stay more time before the conduction of the transistor threshold is too long ramp time may lead to start-up current to continue for a longer time. If the power to the FPGA to provide high current, the longer power-on ramp time can cause heat stress. ADI's DC-DC Regulator provides an adjustable soft-start ramp time can be controlled with an external capacitor. The typical ramp time range from 20ms to 100ms.
Many FPGA timing control requirements, the VCCINT, VCCO and VCCAUX power on. If this is not possible, on the electric current can be slightly higher. Timing requirements vary depending on FPGAs. For the FPGA, to VCCINT and VCCO supply. For others the FPGA power can be connected in any order. In most cases, to give VCCINT VCCO supply is a good practice.
When the VCCINT within the range of 0.6V to 0.8V, some FPGA family will have the power-on inrush current. During this period, the power converter is continuous supply of power. In this application, because the devices need to limit the current by reducing the output voltage, so I do not recommend using foldback current limit. Limiting power solutions, limiting power supply circuit current exceeds the set rated current, and power will the current limit is below the rated value.
FPGA power distribution structure
[Centralized power structure]
Centralized power structure
For high-speed, high-density FPGA devices to maintain good signal integrity is critical to achieve reliable, repeatable design. Proper supply bypassing and decoupling can improve the overall signal integrity. If the decoupling is not fully logical conversion will affect the power and ground voltage, causing the device is not working properly. In addition, the use of distributed power structure is a major solution to the FPGA power supply when the supply voltage offset to a minimum.
In the traditional power structure, AC / DC or DC / DC converter in one place, and provides multiple output voltages, distributed throughout the system. This design is called a centralized power structure (CPA), see left. Allocation of low voltage to high current, the copper wire or PCB track will have a serious resistance loss, the CPA will be a problem.
[Distributed power structure]
Distributed power structure
The alternative of the CPA is the structure of distributed power (DPA), see left. Using the DPA, the entire system only allocated a semi-regulated DC voltage, DC / DC converter (linear or switch mode) is adjacent with the load. DPA, the DC / DC converter and the load (for example, the distance between the FPGA) is much closer, and thus the voltage drop caused by the line resistance and inductance of the wiring can be reduce. This load to provide local power known as the point of load (POL).
Mainstream FPGA technology is still based on the lookup table, has gone far beyond the basic performance of the previous version, and the integration of common functions (such as RAM, clock management, and DSP) hard core (ASIC type) module. Shown in Figure 1-1 (Note: Figure 1-1 is a schematic diagram, in fact, a series FPGA has its own corresponding internal structure), the FPGA chip, Part 7: Programmable input and output unit , the basic programmable logic unit, a complete clock management, embedded block RAM, abundant routing resources, the underlying functional unit of the embedded and embedded in dedicated hardware module.
Figure 1-1 the internal structure of the FPGA chip
Internal structure of the FPGA chip]
The internal structure of the FPGA chip
Each module functions as follows:
A. Programmable input and output units (IOB)
Programmable input / output unit referred to as the I / O unit, the interface part of the chip with the outside circuit, different electrical characteristics on the input / output signals of the drive and match requirements, the matrix structure shown in Figure 1-2. Within the FPGA I / O group classification, each able to independently support different I / O standards. Through the flexible configuration of the software can be adapted to the different electrical standards and I / O physical characteristics, you can adjust the size of the drive current can be changed on the pull-down resistor. At present, the frequency of the I / O port is also getting higher and higher, some high-end FPGA DDR register technology can support data rates up to 2Gbps.
Figure 1-2 Typical IOB internal structure diagram
[IOB internal structure diagram]
IOB internal structure diagram
External input signal can be input to the storage unit through the IOB module inside the FPGA can also be entered directly within the FPGA. When the external input signal input to the FPGA IOB module storage unit internal hold time (Hold Time) requirements can be reduced, usually defaults to 0.
In order to facilitate the management and adapt to a variety of electrical standards, FPGA IOB is divided into several groups (bank), the interface standard for each bank by the interface voltage VCCO, a bank can only be one kind of VCCO is, but different bank the VCCO different. Only the same electrical standard port to connect together, VCCO is voltage the same as the basic conditions of the interface standard.
Two. Configurable logic blocks (the CLB)
CLB is a basic logical unit within the FPGA. The actual number and characteristics of CLB in accordance with the different devices and different, but every CLB contains a configurable switch matrix, this matrix consists of 4 or 6 input, some of the selection circuit (multiplexer, etc.), and triggers composition. Switch matrix is highly flexible and can be configured to handle the combinatorial logic, shift registers or RAM. Xilinx's FPGA devices, the CLB by a number (usually 4 or 2) constitute the same Slice and additional logic shown in Figure 1-3. Each CLB module not only can be used to implement combinational logic, sequential logic, can also be configured as Distributed RAM and Distributed ROM.
Figure 1-3 Typical CLB structure diagram
Typical of the CLB structure diagram]
Typical CLB structure diagram
Slice is the Xilinx defined basic logic unit, its internal structure as shown in Figure 1-4, a Slice by two 4-input function, carry logic, arithmetic logic, memory, logic and function multiplexers. The arithmetic logic includes an XOR gate (XORG) and a dedicated and door (MULTAND,), an XOR gate can make a Slice 2bit All-Canadian operations, with the door used to improve the efficiency of the multiplier; binary logic by special binary signal composition, and function Multiplexer (MUXC), used to implement fast arithmetic addition and subtraction operations; 4-input function generator used to implement 4-input LUT distributed RAM or 16-bit shift register (Virtex-5 family of chips Slice two input function of 6 input, 6-input LUT or 64-bit shift register); binary logic, including two fast carry chain, used to improve the processing speed of the CLB module.
Figure 1-4 Typical 4 Enter the Slice structure diagram
[Typical four-input Slice structure diagram]
4 input Slice Schematic
3. Digital clock management module (DCM)
The industry's most FPGAs provide Digital Clock Management (Xilinx FPGAs have this feature). Xilinx's most advanced FPGAs provide Digital Clock Management and phase loop lock. The phase loop lock can provide precise clock synthesis, and can reduce the jitter, and filtering capabilities.
4. Embedded block RAM (BRAM)
Most FPGAs have embedded block RAM, which greatly expanded the range of applications and flexibility of the FPGA. The block RAM can be configured as a single-port RAM, dual-port RAM, the content address memory (CAM), as well as FIFO and other common storage structure. RAM, the FIFO is a popular concept, this is not redundant references. CAM memory in the internal storage unit has a compare logic and written to the CAM data and internal data, and return the same to the port data of all the data address, thus routing the address The switches have a wide range of applications. In addition to the block RAM, the LUT in the FPGA can be flexibly configured as RAM, ROM, and FIFO structure. In practical applications, the number of chip internal block RAM is to select the chip is an important factor.
Monolithic block RAM capacity of 18k bits, namely bits wide 18 bits, a depth of 1024, according to the need to change the bit-width and depth, but to satisfy two principles: First, the revised capacity (bit wide depth) can not be 18k bits; bit wide maximum not more than 36 bits. Of course, multi-chip block RAM cascaded together to form a larger RAM, limited only by the number of block RAM chip, without the constraints of longer above two principles.
5 Wiring resources
Routing resources connected within the FPGA unit, the length and process connection determines the signal connections on the drive capacity and transmission speed. FPGA chip wiring resources, and divided into four different categories, depending on the process, length, width and distribution of the location. The first category is the global routing resources for the chip internal global clock and global reset / set wiring; The second category is the long-term resources to complete the high-speed signals between chips Bank and the global clock signal wiring; third The class is the short-term resources for the completion of the interconnection and routing of logic between the basic logic unit; The fourth category is a distributed routing resources for a proprietary clock and reset control signal line.
Actual designers do not need to select the routing, placement and routing can be automatically connected to each module unit according to the topology of the input logic netlist and constraints routing resources. In essence, the use of wiring resources and design the result of close, direct relationship.
6. The underlying embedded functional units
Embedded functional modules mainly refers to the DLL (Delay Locked Loop), the PLL (Phase Locked Loop), DSP and CPU soft processing cores (SoftCore). Now more and more embedded functional unit, making the single FPGA as a system-level design tools, to have the hardware and software co-design capabilities, and the gradual transition to the SOC platform.
DLL and PLL has a similar function, you can complete the clock precision, low jitter, multiplication and division, as well as the duty cycle adjustment and shift equivalent function. Integrated the DLL the Xilinx produced chip, Altera Corporation, the chip integrates the PLL, Lattice's new chip integrates a PLL and DLL. PLL and DLL IP core generation tools to easily manage and configure. The structure of the DLL is shown in Figure 1-5.
Figure 1-5 Typical DLL module schematic
[Typical schematic diagram of the DLL module]
A typical schematic diagram of the DLL module
7 embedded dedicated hard-core
Embedded in a dedicated hard core is relatively underlying embedded soft-core, refers to the powerful FPGA processing capability in terms of hard-core (Hard Core), equivalent to ASIC circuit. In order to improve FPGA performance, the chip maker in the chip integrates dedicated hard-core. For example: In order to improve the multiplication speed of the FPGA, the mainstream FPGA integrates a dedicated multiplier; to apply to the communication bus interface standard, many high-end FPGA internal integration of the string and the transceiver (SERDES), can reach tens of Gbps send and receive speeds.
Xilinx's high-end products are not only integrated Power PC series CPU, and embedded DSP the Core module, the corresponding system-level design tools is EDK and Platform Studio, and so the system on a chip (System on Chip) By PowerPC, Miroblaze,, Picoblaze platform, to develop a standard DSP processors and related applications to reach the SOC development purposes.
1) FPGA design ASIC circuit (ASIC), the user does not need to cast film production, you can get a combination of the chip.
2) FPGA can do full custom or semi-custom ASIC circuits in the sample piece.
3) FPGA internal trigger and I / O pins.
4) FPGAs, ASIC circuits in the shortest design cycle, the lowest development costs, one of the smallest device in the risk.
5) FPGA using high-speed CMOS technology, low power consumption, compatible with CMOS, TTL level.
FPGA chip is one of the best small-batch system to improve system integration, reliability.
The FPGA is to set its state by the program stored in the on-chip RAM, therefore, work needs to be programmed on-chip RAM. The user can, depending on the configuration mode, using different programming.
Power, the FPGA chip read the EPROM data programming the RAM into the chip, the configuration is complete, the FPGA into the working state. After power-down, the FPGA restore white film, the internal logic of the relationship disappears, the FPGA can be used repeatedly. FPGA programming without a dedicated FPGA programming, only a universal EPROM, PROM programmer can. When the need to modify the FPGA features, just for an EPROM can be. Thus, the same piece of the FPGA programming data can produce different circuit functions. Therefore, the use of FPGA is very flexible.
(1) the basic problems
FPGA-based digital circuits and HDL language you want to learn FPGA, it is recommended bedside, no matter which version of the book have a digital circuit, this is the foundation, to learn more about that also contribute to the formation of the idea of the hardware design. Language, it is recommended that beginners to learn the Verilog language, VHDL language syntax specification strictly, debugging is very slow, the Verilog language is easy to use, and, generally large enterprises are using Verilog language, VHDL language specification, legibility strong, it is generally military use VHDL.
Familiar with several commonly used development environment, the QuartusII or ISE, the two basically the same, which one would that also is very Easy. Functional simulation suggested use of Modelsim, if you chip, you can learn other simulation tools to do FPGA, Modelsim is sufficient. Synthesis tool for general use Synplify, beginner first should not be too concerned about this, use the Quartus integrated on OK.
(3) the hardware design problem
For beginners, especially from the software, in turn, the design procedures for both fee resources and slow, it is likely that integrated not, which we are familiar with the wording of some fixed modules are integrated module a lot of books. language introduced have, do not take it for granted the idea of software to write hardware.
FPGA learn to practice more and more simulation, signaltapII is a great tool, you can see the true value of each signal is recommended for beginners must own hands, light reading is useless. English documentation, if you want to learn all the features of the Quartus II, as long as its handbook on it in great detail, for the IT industry, most of the sources of knowledge are in English documents, we must be patient to see, from harvest many the.
(5) algorithm issues
FPGA engineer, and finally are generally specialize in the algorithm, these basics are easily pinch, if you are not ready to engage in theoretical preparation, learn FPGA always will remain at the primary stage. For starters, digital signal processing is based on a good understanding, towards a deeper, do not all learn you later engaged in the direction, for example, communications, image processing, radar, sonar, navigation and positioning.
FPGA has a variety of configuration mode: parallel main mode for an FPGA plus an EPROM; master-slave mode multi-chip FPGA can support a PROM Programming; serial mode can use the serial PROM programming the FPGA; peripheral mode the FPGA as a micro- peripherals of the processor, microprocessor programming.
How to achieve rapid timing closure, to reduce power consumption and costs, optimize the clock management and reduce the complexity of issues such as FPGA and PCB concurrent design, has been using the FPGA system designers need to consider the key issues. Now, with the FPGA to the higher density, greater capacity, lower power consumption and integration in the direction of more IP development, system design engineers to benefit from these excellent performance at the same time, have to face the the FPGA unprecedented performance and ability level and the new design challenges.
For example, recently launched by leading FPGA vendors Xilinx Virtex-5 family using 65nm technology can deliver up to 330,000 logic cells, 1,200 I / O and hard IP block. The large capacity and density of the complex wiring becomes more unpredictable, and the resulting more serious problem of timing closure. In addition, the integration for different applications and a larger number of logic functions, DSP, embedded processing and interface modules, clock management and voltage allocation problem becomes more difficult.
Fortunately, the FPGA vendors, EDA tool vendors are working together to solve unique design challenges of 65nm FPGAs. Not long ago, Synplicity and Xilinx announced the formation of large capacity timing closure joint working group designed to help system designers a faster, more efficient application of 65nm FPGA devices. Synthesis tool launched by the design software provider Magma Blast, the FPGA can help to establish an optimized layout, speed up the convergence of timing.
Recently, the FPGA configuration has diversified
Which Altera as the old world of programmable logic device manufacturers, is the inventor of the programmable logic device, development of software MAX + PLUS II and the QuartusII. Xilinx is the inventor of the FPGA, with more than half of the world market, 90% of the high-end 65nmFPGA product development software for the ISE. Actel nonvolatile FPGAs, the products are mainly based on antifuse technology and FLASH technology, its products are mainly used in military and aerospace.
FPGA design precautions
Whether you are a logic designers, hardware engineers or systems engineers, or even to have all these titles, as long as you use in any complex system of a high-speed and multi-protocol FPGA, you most likely need to work to solve the device configuration, power management, IP integration, signal integrity and some key design issues. However, you do not have to alone to face these challenges every day because in the current industry-leading FPGA company's application engineers face these problems, and they have made a number of design guidelines will make your design work has become easier and solutions.
I / O signal allocation
Can provide the most multi-functional pin, I / O standard, termination schemes and differential FPGA signal distribution with the most complex design guidelines. Altera's FPGA device design guidelines (because it implements is easier), but the Xilinx FPGA design guidelines is very complex. But no matter what kind of situation, I / O pin assignment signal, there are some common steps to keep in mind:
A. Use a spreadsheet to list all the plans of the signal distribution, as well as their important properties, such as I / O standard voltage termination method and the associated clock.
Two. Check the manufacturer's / region compatibility guidelines.
. Consider using a spreadsheet to develop the layout of the FPGA to determine which pin is common, and which is dedicated, which support differential signal on the global and local clock, which requires the reference voltage.
4. The use of electronic data table information and regional compatibility criteria, the first allocation of the maximum signal-to-pin restricted extent, the final distribution by the least restrictive. For example, you may need to first be allocated to the serial bus clock signal, because they are usually assigned to specific pins.
5 Redistribution of the signal bus in accordance with the restricted level. At this stage, it may be necessary to carefully weigh the simultaneous switching output (SSO) and is not compatible with the I / O standards, especially when you have a lot of high-speed output, or use several different I / O standards. If your design requires local / regional clock, you will probably need to use high-speed bus near the pin, it is best to remember this request in advance to avoid last can not be arranged by the most appropriate pin. If a particular block the selected I / O standard reference voltage signal, remember to not to assign these pins. The distribution of the differential signal is always first in single-ended signal. If an FPGA chip termination, it may also apply to other compatibility rules.
6. The allocation of the remaining signal in the right place.
At this stage, consider writing an HDL file contains only the port assignment. And then by using the tools provided by the supplier or use a text editor to manually create a restricted file I / O standards and SSO to increase the necessary support information. These documents are ready, you can run the place and route tools to confirm whether to ignore a number of criteria or do a wrong allocation.
This will give you in the initial stages of design and layout engineers to work together to jointly plan the PCB traces, redundancy planning, heat dissipation and signal integrity. FPGA tools may be able to provide assistance in these areas and to help you solve these problems, so you must make sure to understand your toolkit.
You consult a layout expert later time, the more likely you need to deal with complex problems and design iterations, and these may be avoided by some preliminary analysis. Once you achieve a satisfactory signal distribution, you have to limit the file lock.
CMOS-based design is the main consumption of three types of power: internal (short circuit), leakage (static) and switch (capacitor). When the gate transients, short circuit between the VDD and ground connection to internal power consumption. Leakage power CMOS process, a common parasitic effects caused. The switching power is caused by the load capacitance discharge. Switching power and short circuit power consumption together referred to as the dynamic power consumption. Described below to reduce the static power and dynamic power design techniques.
Reduce the static power
Quiescent current compared to the dynamic current can be negligible, however, it is very important for battery-powered handheld devices, especially when the device power instead of working. Quiescent current of many factors, including the I / O and internal operating current of the transistor is not completely shut off or on state, the resistance of the internal connections, enter the three-state electric drive or pull-down resistor. In the volatile technology, to keep the programming information also need a certain amount of static power. The anti-fuse is a nonvolatile technology, the information store is not static current consumption.
Methods to reduce the static power
Driver input should be sufficient voltage level and, therefore, all transistors are completely through conduction or off.
I / O line pull-up or pull-down resistor to consume a certain current, so try to avoid using these resistors.
Less driving resistance or bipolar transistors, these devices need to maintain a constant current, thus increasing the quiescent current.
The clock pin connected to the low parameter list recommended conditions. The floating clock input will be greatly increased quiescent current.
Partition the design into multiple devices, reducing the use of the I / O between devices.
the use of the eX devices LP pin
Actel eX series designed a special low-power "sleep" mode. This pin is driven high 800ns, the device into low power standby mode, the standby current is less than 100μA. Low-power mode, all I / O (In addition to the clock input) in the tri-state, while the kernel is all power outages. Kernel is power failure, the information stored in the flip-flop will be lost into the operating mode (when the pin is driven to low-lying 200ms), the user need to re-initialize the device. Similarly, the user should also close all the input clock CLKA, CLKB, and HCLK. However these clocks are not in the tri-state, the clock can enter into the device, thereby increasing the power consumption in low power mode, the clock input must be at logic 0 or logic 1.
Sometimes difficult for users to stop the clock into the device. On this occasion, the user can use the normal input pin and CLKA CLKA adjacent to add CLKINT in the design. In this way, the clock through the normal input into the device close to the clock pin to clock the device resources by CLKINT.
Using this input circuit, the normal I / O tri-state, so users do not have to worry about the clock into the device. Of course, one door circuit will produce a large clock delay 0.6ns, but fortunately this is acceptable in the majority of low-power design. Note should be related to CLKINT buffer CLKA or CLKB pin grounded.
Moreover, you should, CLKINT can only be used to connect the clock, HCLK does not have the internal alignment of the connections the ability to HCLK, and thus the HCLK resources can not be the conventional input-driven. In other words, if you use the LP pin can not use the HCLK; use HCLK in the external truncated clock signal.
Reduce dynamic power
The dynamic power is the power consumption in clock work and input switch. CMOS circuits, dynamic power is basically to determine the total power consumption. Dynamic power consists of several components, mainly the load capacitance charge and discharge (both internal and I / O) as well as short-circuit current. The most dynamic power is internal or external capacitor to the device to charge and discharge consumption. If the device drivers for multiple I / O load dynamic current constitute the main part of the total power consumption.
Drive a given design, the dynamic power consumption is calculated by
p = CL × V-2 the DD × f
Where CL is the capacitive load, VDD is the supply voltage, f is the switching frequency. The total power consumption is the sum of each drive power.
VDD is fixed to reduce the internal power dissipation is necessary to reduce the average logic switching frequency, reducing the total number of each clock edge at the logic switch to reduce the connection network, in particular, the capacitance value in the high-frequency signal connection network. The design of low power, you need to take appropriate preventive measures from the design level of the system to process, the higher the level, the better.
CPLD identification and classification
FPGA and CPLD identification and classification according to their structural characteristics and working principle. The usual classification is:
Will be the product of structural way constitute a logical behavior of the device called a CPLD, such as Lattice's ispLSI series Xilinx XC9500 series Altera's MAX7000S series and Lattice (formerly Vantis) Mach series.
Will be look-up table structure to constitute a logical behavior of devices called FPGA, such as Xilinx's SPARTAN series, Altera's FLEX10K or ACEX1K series.
FPGA and CPLD are programmable ASIC devices, there are many common characteristics, but because of the difference on CPLD and FPGA architecture, with its own characteristics:
① The CPLD is more suitable to complete a variety of algorithms and combinatorial logic, FP GA is more suitable for the complete temporal logic. In other words, the FPGA is more suitable for the rich structure in the flip-flop, the CPLD is more suitable for limited trigger while the product structure.
② CPLD continuous routing structure determines the timing delay is uniform and predictable, while the FPGA segmented routing structure determines the unpredictability of its delay.
③ in programming FPGAs with greater flexibility than the CPLD. CPLD by modifying the fixed with the circuit logic functions programmable, FPGA, mainly by changing the internal connection of wiring to programming; the FP GA programming logic Ha, the CPLD programming logic block.
④ The FPGA integration than the CPLD has more complex wiring structure and logic to achieve.
⑤ The CPLD than FPGA use more convenient. The CPLD programming E2PROM or FASTFLASH, technology, eliminating the need for an external memory chip, easy to use. FPGA programming information to be stored in external memory, the complexity of the use.
⑥ The CPLD faster than FPGA, and with a greater predictability. This is because the FPGA is a gate-level programming, and the CLB between distributed Internet, the CPLD is a logical block-level programming, and the interconnection between the logic blocks are lumped.
⑦ programmatically, the CPLD is mainly based on E2PROM or FLASH memory programming, programming up to 10,000 times the number, the advantages of programming information is not lost when the system is powered down. The CPLD can be divided into two types of programming in the programmer and in-system programming. FPGA is based on SRAM programming, the programming information in the system when power is lost, each power devices external to programming data to re-write the SRAM. Its advantages can be programmed any time, fast programming at work, in order to achieve the dynamic configuration of the board and system level.
⑧ the CPLD confidentiality, poor FPGA confidentiality.
⑨The general case, the CPLD power consumption than FPGAs, and the integration degrees higher.
A. Circuit design applications
Connection logic, control logic is FPGA early role of the relatively large areas are also the cornerstone of the FPGA application. In fact the difficulty in circuit design using FPGA is quite large This requires developers to have knowledge of the hardware (circuit knowledge) and software applications (development tools) in this area is always scarce, and often engaged in new technology